Accenture Physical Design Engineer in Florham Park, New Jersey
The Silicon Design group is a diverse team of world class silicon engineers. We have 100+ years of cumulative hands-on experience in architecture, logic design, verification, physical design, emulation and firmware. We use the latest silicon technologies and processes to help our clients create well-designed solutions to highly complex challenges. We are designing and developing next-generation, high performance SoCs, supporting our clients in their drive to deliver their product vision to their users. We are involved in all aspects of chip design from definition and architecture through to verification and signoff. Accenture engineers are true “Silicon to SW” Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market.
An experienced Physical Design Engineer
Develop own physical design implementation of multi hierarchy low power designs including physical aware logic synthesis, design for testability, static timing analysis, power analysis, IR Drop, EM, in advanced technology nodes
Resolve power issues related to physical design, identify potential low power solutions, drive execution and methodology improvements
Perform comprehensive power analysis in vector and vector-less modes of ASIC SoC design
Here’s what you need:
A minimum of three years of experience with:
RTL2GDSllon advanced technology nodes (7nm and below)
Low power implementation and signoff, power gating, multiple voltage rails, UPF/CPF.
Power constraints generation and validation, power analysis, interface with power integrity analysis tools.
TCL, Python and/or Perl programming
EDA tools like DesignCompiler/Genus, Primetime/PrimePower, ICC2/Innovus, Redhawk/Voltus
Bachelor’s Degree or equivalent (12 years) work experience (If an, Associate’s Degree with 6 years of work experience)
Bonus points if:
Experience running power analysis in vector and vector-less modes and achieving optimal QoR on low power designs
Knowledge of static timing analysis, power analysis and concepts, defining timing and power constraints exceptions, switching activity definitions and simulation vectors
Experience with power integrity analysis at block level or top level, including EM, IR & ESD analysis, power reduction techniques in SOC design
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