Accenture Design Verification and Gate Level Simulation Principal Engineer in Florham Park, New Jersey
The Silicon Design group is a diverse team of world class silicon engineers. We have 100+ years of cumulative hands-on experience in architecture, logic design, verification, physical design, emulation and firmware. We use the latest silicon technologies and processes to help our clients create well-designed solutions to highly complex challenges. We are designing and developing next-generation, high performance SoCs, supporting our clients in their drive to deliver their product vision to their users. We are involved in all aspects of chip design from definition and architecture through to verification and signoff. Accenture engineers are true “Silicon to SW” Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market.
An experienced SoC Design Verification Engineer able to provide design verification services for multi CPU/DSP SoC.
Testbench development - System Verilog UVM and C tests
Integration/development of C tests/APIs and SW build flow
Integration/development of UVM mailboxes and HW/SW communication components
Run tests on RTL and Gate level Netlists, debug failures to root cause and recommend fixes
Test plan development
Power Aware testbench development and simulations
Seamless porting between simulation/emulation/prototyping platforms
Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto
Coverage collection and closure
Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope
Engage with the team to drive continuous improvement to the verification environment to find more bugs and improve coverage
Work as a team to grow together.
Mentor and coach junior team members
Here’s what you need:
A minimum of five years of experience with Gate-Level Simulation
Bachelor’s Degree or equivalent (12 years) work experience (If an Associate’s Degree with 6 years of work experience)
Bonus points if:
Expertise with debugging in Best/Worst SDF with min/max corner simulations
Understanding of various timing violations and identifying them as waiver or real netlist issues by working closely with design and architecture teams
Experience with timing constraints and multi clock domain design
Experience with Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes
Experience with Power-Aware simulation
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